`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:01:41 02/22/2011 
// Design Name: 
// Module Name:    NbitAdder 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module NbitAdder #(parameter N=8) (
    input [N-1:0] a_in,
    input [N-1:0] b_in,
    input c_in,
    output [N-1:0] s_out,
    output c_out
    );
	 
	 wire[N-2:0] carry;
	 
	 genvar i;
	 generate
		for(i=0; i<N; i=i+1) begin: adders
			if(i==0) begin
				fullAdder a(a_in[i], b_in[i], c_in, s_out[i], carry[i]);
			end else if (i == N-1) begin
				fullAdder a(a_in[i], b_in[i], carry[i-1], s_out[i], c_out);
			end else begin
				fullAdder a(a_in[i], b_in[i], carry[i-1], s_out[i], carry[i]);
			end
		end
	endgenerate


endmodule
